© 2004 Microchip Technology Inc. DS70074C-page 26-11
Section 26. Appendix
Appendix
26
Table A-3: I
2
C Bus Data Timing Specification
Parameter
No.
Sym Characteristic Min Max Units Conditions
100 T
HIGH Clock high time 100 kHz mode 4.0 — µs
400 kHz mode 0.6 — µs
101 T
LOW Clock low time 100 kHz mode 4.7 — µs
400 kHz mode 1.3 — µs
102 T
R SDA and SCL rise
time
100 kHz mode — 1000 ns
400 kHz mode 20 +
0.1Cb
300 ns Cb is specified to be from
10 to 400 pF
103 T
F SDA and SCL fall
time
100 kHz mode — 300 ns
400 kHz mode 20 +
0.1Cb
300 ns Cb is specified to be from
10 to 400 pF
90 T
SU:STA Start condition setup
time
100 kHz mode 4.7 — µs Only relevant for repeated
Start condition
400 kHz mode 0.6 — µs
91 T
HD:STA Start condition hold
time
100 kHz mode 4.0 — µs After this period the first
clock pulse is generated
400 kHz mode 0.6 — µs
106 T
HD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107 T
SU:DAT Data input setup time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
92 T
SU:STO Stop condition setup
time
100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109 T
AA Output valid from
clock
100 kHz mode — 3500 ns Note 1
400 kHz mode — 1000 ns
110 T
BUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — µs
D102 Cb Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode I
2
C-bus device can be used in a Standard mode I
2
C-bus system, but the requirement
T
SU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line,
T
R max.+TSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification) before
the SCL line is released.
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