© 2004 Microchip Technology Inc. DS70050C-page 3-19
Section 3. Data Memory
Data Memory
3
Register 3-1: MODCON: Modulo and Bit-Reversed Addressing Control Register
Upper Byte:
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
XMODEN YMODEN — — BWM<3:0>
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
YWM<3:0> XWM<3:0>
bit 7 bit 0
bit 15 XMODEN: X RAGU and X WAGU Modulus Addressing Enable bit
1 = X AGU modulus addressing enabled
0 = X AGU modulus addressing disabled
bit 14 YMODEN: Y AGU Modulus Addressing Enable bit
1 = Y AGU modulus addressing enabled
0 = Y AGU modulus addressing disabled
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 BWM<3:0>: X WAGU Register Select for Bit-Reversed Addressing bits
1111 = Bit-reversed addressing disabled
1110 = W14 selected for bit-reversed addressing
1101 = W13 selected for bit-reversed addressing
•
•
0000 = W0 selected for bit-reversed addressing
bit 7-4 YWM<3:0>: Y AGU W Register Select for Modulo Addressing bits
1111 = Modulo addressing disabled
1010 = W10 selected for modulo addressing
1011 = W11 selected for modulo addressing
Note: All other settings of the YWM<3:0> control bits are reserved and should not be used.
bit 3-0 XWM<3:0>: X RAGU and X WAGU W Register Select for Modulo Addressing bits
1111 = Modulo addressing disabled
1110 = W14 selected for modulo addressing
•
•
0000 = W0 selected for modulo addressing
Note: A write to the MODCON register should not be followed by an instruction that performs an
indirect read operation using a W register. Unexpected results may occur. Some instructions
perform an implicit indirect read. These are: POP, RETURN, RETFIE, RETLW and ULNK.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown