© 2004 Microchip Technology Inc. DS70050C-page 3-21
Section 3. Data Memory
Data Memory
3
Register 3-4: YMODSRT: Y AGU Modulo Addressing Start Register
Register 3-5: YMODEND: Y AGU Modulo Addressing End Register
Upper Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
YS<15:8>
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
YS<7:1>
0
bit 7 bit 0
bit 15-1 YS<15:1>: Y AGU Modulo Addressing Start Address bits
bit 0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Upper Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
YE<15:8>
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1
YE<7:1>
1
bit 7 bit 0
bit 15-1 YE<15:1>: Y AGU Modulo Addressing End Address bits
bit 0 Unimplemented: Read as ‘1’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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