RL78/G1H CHAPTER 6 CLOCK GENERATOR
R01UH0575EJ0120 Rev. 1.20 Page 107 of 920
Dec 22, 2016
Figure 6 - 5 Format of Oscillation stabilization time counter status register (OSTC)
Caution 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1.
Caution 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the
oscillation stabilization time select register (OSTS).
In the following cases, set the oscillation stabilization time of the OSTS register to the value greater
than the count value which is to be checked by the OSTC register.
• When the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem
clock is being used as the CPU clock.
• When the STOP mode is entered and then released while the high-speed on-chip oscillator clock is
being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register
is set to the OSTC register after the STOP mode is released.)
Caution 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts
(“a” below).
Remark
fX: X1 clock oscillation frequency
Address: FFFA2H After reset: 00H R
Symbol76543210
OSTC MOST8 MOST9
MOST
10
MOST
11
MOST
13
MOST
15
MOST
17
MOST
18
MOST
8
MOST
9
MOST
10
MOST
11
MOST
13
MOST
15
MOST
17
MOST
18
Oscillation stabilization time status
f
X = 10 MHz fX = 20 MHz
00000000
2
8
/fX max.
25.6
μs max. 12.8 μs max.
10000000
2
8
/fX min.
25.6
μs min. 12.8 μs min.
11000000
2
9
/fX min.
51.2
μs min. 25.6 μs min.
11100000
2
10
/fX min.
102
μs min. 51.2 μs min.
11110000
2
11
/fX min.
204
μs min. 102 μs min.
11111000
2
13
/fX min.
819
μs min. 409 μs min.
11111100
2
15
/fX min.
3.27 ms min. 1.63 ms min.
11111110
2
17
/fX min.
13.1 ms min. 6.55 ms min.
11111111
2
18
/fX min.
26.2 ms min. 13.1 ms min.
STOP mode release
X1 pin voltage
waveform
a
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