RL78/G1H CHAPTER 6 CLOCK GENERATOR
R01UH0575EJ0120 Rev. 1.20 Page 111 of 920
Dec 22, 2016
Figure 6 - 8 Format of Peripheral enable register 0 (PER0) (2/3)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PER0 RTCEN
IICA1EN
ADCEN IICA0EN SAU1EN SAU0EN
TAU1EN
TAU0EN
IICA1EN
Control of serial interface IICA1 input clock supply
0 Stops input clock supply.
• SFR used by the serial interface IICA1 cannot be written.
• The serial interface IICA1 is in the reset status.
1 Enables input clock supply.
• SFR used by the serial interface IICA1 can be read and written.
ADCEN Control of A/D converter input clock supply
0 Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1 Enables input clock supply.
• SFR used by the A/D converter can be read and written.
IICA0EN Control of serial interface IICA0 input clock supply
0 Stops input clock supply.
• SFR used by the serial interface IICA0 cannot be written.
• The serial interface IICA0 is in the reset status.
1 Enables input clock supply.
• SFR used by the serial interface IICA0 can be read and written.
SAU1EN Control of serial array unit 1 input clock supply
0 Stops input clock supply.
• SFR used by the serial array unit 1 cannot be written.
• The serial array unit 1 is in the reset status.
1 Enables input clock supply.
• SFR used by the serial array unit 1 can be read and written.
SAU0EN Control of serial array unit 0 input clock supply
0 Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
1 Enables input clock supply.
• SFR used by the serial array unit 0 can be read and written.