RL78/G1H CHAPTER 6 CLOCK GENERATOR
R01UH0575EJ0120 Rev. 1.20 Page 112 of 920
Dec 22, 2016
Figure 6 - 9 Format of Peripheral enable register 0 (PER0) (3/3)
Address: F00F0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PER0
RTCEN
IICA1EN
ADCEN IICA0EN SAU1EN SAU0EN
TAU1EN
TAU0EN
TAU1EN
Control of timer array unit 1 input clock supply
0 Stops input clock supply.
• SFR used by timer array unit 1 cannot be written.
• Timer array unit 1 is in the reset status.
1 Enables input clock supply.
• SFR used by timer array unit 1 can be read and written.
TAU0EN Control of timer array unit 0 input clock supply
0 Stops input clock supply.
• SFR used by timer array unit 0 cannot be written.
• Timer array unit 0 is in the reset status.
1 Enables input clock supply.
• SFR used by timer array unit 0 can be read and written.