RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 143 of 920
Dec 22, 2016
Figure 7 - 1 Entire Configuration of Timer Array Unit 0
Remark fSUB: Subsystem clock frequency
f
IL: Low-speed on-chip oscillator clock frequency
Channel 1
Channel 0
INTTM00
(Timer interrupt)
TAU0EN
fSUB
Prescaler
Timer clock select register 0 (TPS0)
fCLK/2
1
, fCLK/2
2
,
f
CLK/2
4
, fCLK/2
6
fCLK/2
0
to fCLK/2
15
PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
2 2
4
4
SelectorSelector
Selector
Selector
fCLK/2
8
, fCLK/2
10
,
f
CLK/2
12
, fCLK/2
14
Channel 2
Channel 3
INTTM01
INTTM01H
INTTM02
TO03
INTTM03
INTTM03H
fIL
Timer input select
register 0 (TIS0)
TIS04 TIS02 TIS01 TIS00
Peripheral
enable
register 0
(PER0)
f
CLK
Event input
from ELC
SelectorSelector
Event input
from ELC
CK03 CK02 CK01 CK00
TI03
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