Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 144 of 920
Dec 22, 2016
Figure 7 - 2 Internal Block Diagram of Channel 0 of Timer Array Unit 0
Figure 7 - 3 Internal Block Diagram of Channel 1 of Timer Array Unit 0
Mode
selection
Timer
controller
Edge
detection
Timer mode register 00 (TMR00)
OVF00
Channel 0
CK00
CK01
Timer counter register 00 (TCR00)
Timer data register 00 (TDR00)
CKS000 CCS00
0
STS002STS001STS000 CIS001 CIS000 MD003 MD002 MD001 MD000
INTTM00 (Timer interrupt)
Interrupt controller
Timer status
register 00 (TSR00)
Overflow
fMCK
fTCLK
Operating clock
selection
Count clock
selection
Trigger
selection
CKS001
Selector
TIS04 TIS02 TIS01 TIS00
Timer input select
register 0 (TIS0)
Event input
from ELC
Interrupt signal to slave channel
Noise
filter
TNFEN00
Noise filter
enable register 1
(NFEN1)
Mode
selection
Timer
controller
INTTM01H (Timer interrupt)
Interrupt controller
OVF01
Interrupt controller
CK00
CK01
CK02
CK03
Edge
detection
fMCK
Operating clock
selection
Count clock
selection
Trigger
selection
Interrupt signal from master channel
Timer mode register 01 (TMR01)
CKS010 CCS01
SPLIT
01
STS012STS011STS010 CIS011 CIS010 MD013 MD012 MD011 MD010
Mode
selection
8-bit timer
controller
INTTM01 (Timer interrupt)
Timer status register
01 (TSR01)
Overflow
fTCLK
Channel 1
CKS011
Selector
fIL
TIS04TIS02TIS01TIS00
Timer input select
register 0 (TIS0)
Timer counter register 01 (TCR01)
Timer data register 01 (TDR01)
fSUB
Event input
from ELC
Noise
filter
TNFEN01
Noise filter
enable register 1
(NFEN1)

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English