RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 176 of 920
Dec 22, 2016
(2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1)
The count clock (f
TCLK) becomes the signal that detects valid edge of input signal via the TImn pin and
synchronizes next rising fMCK. The count clock (fTCLK) is delayed for 1 to 2 period of fMCK from the input
signal via the TImn pin (when a noise filter is used, the delay becomes 3 to 4 clock).
Counting of timer count register mn (TCRmn) delayed by one period of f
CLK from rising edge of the count
clock, because of synchronization with fCLK. But, this is described as “counting at valid edge of input signal
via the TImn pin”, as a matter of convenience.
Figure 7 - 27 Timing of f
CLK and count clock (fTCLK) (When CCSmn = 1, noise filter unused)
<1> Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input signal via the
TImn pin.
<2> The rise of input signal via the TImn pin is sampled by f
MCK.
<3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output.
Remark 1. : Rising edge of the count clock
: Synchronization, increment/decrement of counter
Remark 2. fCLK: CPU/peripheral hardware clock
f
MCK: Operation clock of channel n
Remark 3. The waveform of the input signal via TImn pin of the input pulse interval measurement, the measurement of
high/low width of input signal, and the delay counter function are the same as that shown in Figure 7 - 27.
fCLK
fMCK
TSmn (Write)
TEmn
TImn input
Sampling wave
Rising edge detection
signal (f
TCLK)
<1>
<2>
<3>
Edge detection Edge detection
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