RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 181 of 920
Dec 22, 2016
(4) Operation of one-count mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn
register and count starts.
<5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the
value of the TCRmn register becomes FFFFH and counting stops.
Figure 7 - 31 Operation Timing (In One-count Mode)
Remark The timing is shown in Figure 7 - 31 indicates while the noise filter is not used. By making the noise filter on-
state, the edge detection becomes 2 f
MCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of
TImn input. The error per one period occurs be the asynchronous between the period of the TImn input and
that of the count clock (f
MCK).
fMCK
(fTCLK)
TSmn (Write)
TEmn
TImn input
Rising edge
Start trigger
detection signal
<1>
<2>
<4>
TCRmn
INTTMmn
<3>
Initial value 1 FFFF
m 0
Edge detection
<5>
Start trigger input wait
status
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