RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 180 of 920
Dec 22, 2016
(3) Operation of capture mode (input pulse interval measurement)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
<3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H
is loaded to the TCRmn register and counting starts in the capture mode. (When the MDmn0 bit is
set to 1, INTTMmn is generated by the start trigger.)
<4> On detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer
data register mn (TDRmn) and INTTMmn is generated. However, this capture value is no meaning.
The TCRmn register keeps on counting from 0000H.
<5> On next detection of the valid edge of the TImn input, the value of the TCRmn register is captured to
timer data register mn (TDRmn) and INTTMmn is generated.
Figure 7 - 30 Operation Timing (In Capture Mode: Input Pulse Interval Measurement)
Note If a clock has been input to TImn (the trigger exists) when capturing starts, counting starts when a trigger is
detected, even if no edge is detected. Therefore, the first captured value (<4>) does not determine a pulse
interval (in the above figure, 0001 just indicates two clock cycles but does not determine the pulse interval) and
so the user can ignore it.
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by setting
MDmn0 = 1.
Remark
The timing is shown in Figure 7 - 30 indicates while the noise filter is not used. By making the noise filter on-
state, the edge detection becomes 2 f
MCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of
TImn input. The error per one period occurs be the asynchronous between the period of the TImn input and
that of the count clock (f
MCK).
0000
fMCK
(fTCLK)
TSmn (Write)
TEmn
TImn input
Rising edge
Start trigger
detection signal
<1>
<2>
<4>
TCRmn
TDRmn
<3>
<3>
Initial value
m - 1 0000
INTTMmn
<5>
0001 0000 m
0001
Note
m
When MDmn0 = 1
Edge detection
Edge detection
Note
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