RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 195 of 920
Dec 22, 2016
Figure 7 - 42 Block Diagram of Operation as Interval Timer/Square Wave Output
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2, and CKm3.
Figure 7 - 43 Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MDmn0 = 1)
Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
TOmn: TOmn pin output signal
Timer counter
register mn (TCRmn)
Interrupt
controller
TOmn pin
Interrupt signal
(INTTMmn)
Timer data
register mn (TDRmn)
Output
controller
TSmn
Operation clock
Note
CKm0
CKm1
Clock selectionTrigger selection
TSmn
TEmn
TDRmn
TCRmn
TOmn
INTTMmn
a
a + 1
b
0000H
a + 1 a + 1 b + 1 b + 1 b + 1