RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 196 of 920
Dec 22, 2016
Figure 7 - 44 Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2)
(a) Timer mode register mn (TMRmn)
(b) Timer output register m (TOm)
(c) Timer output enable register m (TOEm)
(d) Timer output level register m (TOLm)
(e) Timer output mode register m (TOMm)
Note TMRm2: MASTERmn bit
TMRm1, TMRm3: SPLITmn bit
TMRm0: Fixed to 0
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
1514131211109876543210
TMRmn
CKSmn1
1/0
CKSmn0
1/0 0
CCSmn
0
M/S
Note
0/1
STSmn2
0
STSmn1
0
STSmn0
0
CISmn1
0
CISmn0
000
MDmn3
0
MDmn2
0
MDmn1
0
MDmn0
1/0
Operation mode of
channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
1: Generates INTTMmn and inverts timer
output when counting is started.
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Setting of MASTERmn bit (channel 2)
0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3)
0: 16-bit timer mode
1: 8-bit timer mode
Count clock selection
0: Selects operation clock (f
MCK).
Operation clock (f
MCK) selection
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected using channels 1 and 3 in the 8-bit timer mode).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected using channels 1 and 3 in the 8-bit timer mode).
Bit n
TOm
TOmn
1/0
0: Outputs 0 from TOmn.
1: Outputs 1 from TOmn.
Bit n
TOEm
TOEmn
1/0
0: Stops the TOmn output operation by counting operation.
1: Enables the TOmn output operation by counting operation.
Bit n
TOLm
TOLmn
0
0: Cleared to 0 when TOMmn = 0 (master channel output mode)
Bit n
TOMm
T
OMmn
0
0: Sets master channel output mode.