RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 200 of 920
Dec 22, 2016
Figure 7 - 48 Example of Basic Timing of Operation as External Event Counter
Remark 1. m: Unit number (m = 0), n: Channel number (n = 3)
Remark 2. TSmn: Bit n of timer channel start register m (TSm)
TEmn: Bit n of timer channel enable status register m (TEm)
TImn: TImn pin input signal
TCRmn: Timer count register mn (TCRmn)
TDRmn: Timer data register mn (TDRmn)
TSmn
TEmn
TImn
TDRmn
TCRmn
INTTMmn
0003H 0002H
3
2
1
0
3
2
1
0
2
1
0
2
1
0000H
4 events 4 events 3 events