Renesas RL78/G1H

RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 216 of 920
Dec 22, 2016
Figure 7 - 63 Block Diagram of Operation as PWM Function
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2)
p: Slave channel number (p = 3)
Interrupt
controller
Interrupt signal
(INTTMmn)
Timer data
register mn (TDRmn)
Operation clock
CKm0
CKm1
Timer counter
register mn (TCRmn)
TSmn
Interrupt
controller
Interrupt signal
(INTTMmp)
Timer data
register mp (TDRmp)
Operation clock
CKm0
CKm1
Timer counter
register mp (TCRmp)
Master channel
(interval timer mode)
Slave channel
(one-count mode)
Output
controller
TOmp pin
Clock selectionTrigger selectionClock selectionTrigger selection