RL78/G1H CHAPTER 13 A/D CONVERTER
R01UH0575EJ0120 Rev. 1.20 Page 321 of 920
Dec 22, 2016
Figure 13 - 31 Timing of A/D Conversion End Interrupt Request Generation
(8) Conversion results just after A/D conversion start
While in the software trigger mode or hardware trigger no-wait mode, the first A/D conversion value immediately
after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 μs after the
ADCE bit was set to 1. Take measures such as polling the A/D conversion end interrupt request (INTAD) and
removing the first conversion result.
(9) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to A/D converter mode register 0 (ADM0), analog input channel
specification register (ADS), A/D port configuration register (ADPC), and port mode control register (PMCxx), the
contents of the ADCR and ADCRH registers may become undefined. Read the conversion result following
conversion completion before writing to the ADM0, ADS, ADPC, or PMC register. Using a timing other than the
above may cause an incorrect conversion result to be read.
ANIn
ANIn ANIn ANIm ANIm
ANIn ANIm ANImA/D conversion
ADCR
ADIF
ADS rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
ADS rewrite
(start of ANIn conversion)
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