RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 416 of 920
Dec 22, 2016
(1) Register setting
Figure 14 - 80 Example of Contents of Registers for UART Reception of UART (UARTq) (1/2)
(a) Serial mode register mn (SMRmn)
(b) Serial mode register mr (SMRmr)
(c) Serial communication operation setting register mn (SCRmn)
(d) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
Caution For the UART reception, be sure to set the SMRmr register of channel r that is to be paired with
channel n.
Remark 1.
q: UART number (q = 1, 3), r: Channel number (r = n − 1)
Remark 2. : Setting is fixed in the UART reception mode,
: Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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SMRmn
CKSmn
0/1
CCSmn
0
0 0 0 0 0
STSmn
1 0
SISmn0
0/1 1 0 0 0
MDmn1
1
MDmn0
0
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0
set by the SPSm register
1: Prescaler output clock CKm1
set by the SPSm register
0: Forward (normal) reception
1: Reverse reception
Operation mode of channel n
0: Transfer end interrupt
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SMRmr
CKSmr
0/1
CCSmr
0
0 0 0 0 0 0 0 0 1 0 0 0
MDmr1
1
MDmr0
0/1
Same setting value as CKSmn bit Operation mode of channel r
0: Transfer end interrupt
1: Buffer empty interrupt
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SCRmn
TXEmn
0
RXEmn
1
DAPmn
0
CKPmn
0
0
EOCmn
1
PTCmn1
0/1
PTCmn0
0/1
DIRmn
0/1 0
SLCmn1
0
SLCmn0
1 0 1 1
DLSmn0
0/1
Setting of parity bit
00B: No parity
01B: No parity judgment
10B: Appending Even parity
11B: Appending Odd parity
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first
Setting of data
length
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SDRmn Baud rate setting
0
Receive data register
RXDq
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