RL78/G1H CHAPTER 14 SERIAL ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 418 of 920
Dec 22, 2016
(2) Operation procedure
Figure 14 - 82 Initial Setting Procedure for UART Reception
Caution Set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after 4 or more fMCK
clocks have elapsed.
Figure 14 - 83 Procedure for Stopping UART Reception
Release the serial array unit from the reset status
and start clock supply.
Setting the PER0 register
Starting initial setting
Setting the SPSm register
Setting the SMRmn and SMRmr registers
Setting the SCRmn register
Setting the SDRmn register
Writing to the SSm register
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the transfer clock
by dividing the operation clock (f
MCK)).
Set the SSmn bit of the target channel to 1 and set
the Semn bit to 1 (to enable operation).
Become wait for start bit detection.
Completing initial setting
Setting port
Enable data input of the target channel by setting a
port register and a port mode register.
Write 1 to the STmn bit of the target channel.
(SEmn = 0: to operation stop status)
Writing the STm register
Starting setting to stop
Completing initial setting
After the stop setting is completed, go to the next
processing.
Setting the PER0 register
Reset the serial array unit by stopping the clock
supply to it.
(Selective)
(Essential)
TSFmn = 0?
No
If there is any data being transferred,
wait for their completion.
(If there is an urgent must stop, do not wait).
Yes
(Selective)
To Next Page
Loading...
Need help?
General
