RL78/G1H CHAPTER 15 SERIAL INTERFACE IICA
R01UH0575EJ0120 Rev. 1.20 Page 436 of 920
Dec 22, 2016
Figure 15 - 7 Format of IICA control register n0 (IICCTLn0) (2/4)
Note 1. The signal of this bit is invalid while IICEn is 0. Set this bit during that period.
Note 2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated regardless of
the set value.
Remark n = 0, 1
SPIEn
Note 1
Enable/disable generation of interrupt request when stop condition is detected
0 Disable
1 Enable
If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn =
1.
Condition for clearing (SPIEn = 0) Condition for setting (SPIEn = 1)
• Cleared by instruction
• Reset
• Set by instruction
WTIMn
Note 1
Control of wait and interrupt request generation
0 Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1 Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this
bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the
falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is
inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device
has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIMn = 0) Condition for setting (WTIMn = 1)
• Cleared by instruction
• Reset
• Set by instruction
ACKEn
Notes 1, 2
Acknowledgment control
0 Disable acknowledgment.
1 Enable acknowledgment. During the ninth clock period, the SDAAn line is set to low level.
Condition for clearing (ACKEn = 0) Condition for setting (ACKEn = 1)
• Cleared by instruction
• Reset
• Set by instruction
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