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General| Core Architecture | RL78 |
|---|---|
| Maximum Operating Frequency | 32 MHz |
| Flash Memory | Up to 128 KB |
| Temperature Range | -40°C to +85°C |
| ADC | 12-bit ADC |
| Communication Interfaces | UART, I2C |
| D/A Converter | No |
| Bluetooth | No |
| Package | LQFP |
| Timers | 16-bit Timer x 8, 12-bit Interval Timer x 1 |
Details the key features including low power consumption, CPU core, on-chip RF transceiver, and memory capabilities.
Provides information on how to order the RL78/G1H microcontroller, including part numbers and package types.
Illustrates the pin layout of the 64-pin plastic HVQFN package for the RL78/G1H.
Identifies and describes the function of each MCU and RF transceiver unit pin.
Shows the overall block diagram of the RL78/G1H, illustrating the MCU and RF parts.
Summarizes the key functions of the RL78/G1H, including memory, I/O ports, timers, and RF transceiver.
Lists internal and external pin connections between the MCU and RF transceiver.
Details the 3-wire serial I/O (CSI) interface used for internal communication between MCU and RF unit.
Specifies the initial output mode settings for unused internal MCU pins after reset.
Explains the requirement for a 48 MHz clock for RF unit operation and its connection.
Illustrates the power configuration of the RL78/G1H, including the DC-DC converter for the RF unit.
Provides a diagram showing the connection of peripheral circuits for the RL78/G1H.
Describes the I/O buffer power supplies and pin I/O buffer configurations based on pin types.
Lists functions of pins that are not standard I/O ports, such as analog input, reset, and clock pins.
Provides recommended connections for unused pins to prevent floating or unexpected behavior.
Illustrates the block diagrams for different pin types, showing internal circuitry.
Details the 1 MB address space of the RL78/G1H, including program and data memory maps.
Describes the processor registers, including control registers and general-purpose registers.
Explains the digital I/O ports and their alternate functions, referring to Chapter 3 for details.
Lists the hardware components related to port configuration, including various registers and port counts.
Lists registers used to control port functions, such as port mode registers and pull-up resistor option registers.
Explains port operations, differentiating between output mode and input mode.
Provides basic concepts and examples for setting registers when using alternate pin functions.
Highlights important cautions for using port functions, especially regarding 1-bit manipulation and pin settings.
Explains the role of the clock generator in supplying clocks to the CPU and peripheral hardware.
Details the hardware components included in the clock generator.
Lists registers used to control the clock generator's operation mode and status.
Describes the X1 oscillator, XT1 oscillator, high-speed on-chip oscillator, and low-speed on-chip oscillator.
Explains how the clock generator operates and controls CPU and standby modes.
Provides examples and procedures for setting up and controlling various clock sources.
Details the functions of the timer array unit, including independent and simultaneous channel operations.
Lists the hardware components included in the timer array unit.
Lists registers used to control the timer array unit's functions.
Explains basic rules for simultaneous channel and 8-bit timer operations.
Describes how the counter operates, including count clock selection and timing.
Explains the control of channel outputs to the TOmn pin, including circuit configuration and setting examples.
Details the TImn input circuit configuration and noise filter usage.
Describes various independent channel operation functions like interval timer and event counter.
Explains simultaneous channel operations, specifically the PWM output function.
Provides cautions for using timer output and input operations to prevent issues.
Introduces Timer RJ as a 16-bit timer with reload and down counter, listing its specifications.
Shows the block diagram and configuration of Timer RJ.
Lists the registers used to control the Timer RJ peripheral.
Explains Timer RJ operation modes, reload register, and coordination with ELC.
Provides cautions for using Timer RJ, including start/stop control and mode changes.
Lists the features of the real-time clock, including counter ranges and interrupt functions.
Details the hardware components included in the real-time clock.
Lists the registers used to control the real-time clock.
Explains the operation of the real-time clock, including starting, stopping, and reading/writing.
Describes the interrupt generation at specified time intervals for wakeup and A/D converter SNOOZE mode.
Lists the hardware components included in the 12-bit interval timer.
Lists the registers used to control the 12-bit interval timer.
Explains the operation timing of the 12-bit interval timer for generating interrupts.
Explains the function of the clock output controller for peripheral ICs and buzzer output.
Lists the hardware components of the clock output/buzzer output controller.
Lists the registers used to control the clock output/buzzer output controller.
Explains the operation of the clock output/buzzer output controller, specifically as an output pin.
Provides cautions related to clock output and buzzer output operations.
Explains the watchdog timer's function in detecting program loops and generating internal reset signals.
Details the hardware components of the watchdog timer and how its operation is controlled by the option byte.
Identifies the watchdog timer enable register (WDTE) for controlling the watchdog timer.
Explains how to control the watchdog timer's operation, including enabling, setting overflow time, and window open period.
Describes the A/D converter's function of converting analog input signals to digital values.
Lists the hardware components of the A/D converter.
Lists registers used to control the A/D converter's mode, results, and port functions.
Explains the A/D converter's conversion operations, including trigger modes and sampling.
Shows the relationship between analog input voltage and theoretical A/D conversion results.
Details various A/D converter operation modes, including software trigger and hardware trigger modes.
Provides flowcharts for setting up software trigger, hardware trigger no-wait, and hardware trigger wait modes.
Explains the SNOOZE mode function for A/D conversion triggered by hardware or ELC events.
Lists important cautions for using the A/D converter, covering operating current, conflicting operations, and noise countermeasures.
Describes the serial array unit's communication capabilities, including 3-wire serial I/O and UART.
Lists the hardware components of the serial array unit.
Lists registers used to control the serial array unit's functions.
Explains how to stop the operation of serial array units by units or channels.
Details the CSIp communication, including data transfer, clock control, and interrupt functions.
Explains UART communication, covering data transmission, reception, and error detection.
Describes the three modes of serial interface IICA: operation stop, I2C bus, and wakeup modes.
Lists the hardware components of the serial interface IICA.
Lists the registers used to control the serial interface IICA.
Details pin configurations and functions related to the I2C bus mode.
Explains I2C bus definitions and control methods, including start conditions, addresses, and ACK.
Shows timing charts for I2C bus operations, including arbitration and interrupt request timing.
Explains the DTC's function of transferring data between memories without CPU intervention.
Shows the DTC block diagram and its configuration.
Lists registers used to control the DTC, including enable, control, and address registers.
Explains DTC operation modes, including normal and repeat modes, and transfer sizes.
Provides cautions for using the DTC, covering control data allocation and access.
Describes the ELC's function of linking peripheral events for coordinated operation.
Shows the ELC block diagram.
Lists registers used to control the ELC, specifically the event output destination select register.
Explains the ELC setting procedure for starting and stopping operations.
Provides an overview of the RF transceiver, its features, frequency range, and modulation methods.
Describes the digital and analog pin functions of the RF unit.
Details the configuration of the RF transceiver, including analog block, digital block, and power supply.
Explains the baseband function, including configuration, frame control, and interrupts.
Describes the serial interface used for internal communication between the MCU and RF transceiver.
Classifies the RF operating modes into three types: transmission, reception, and IDLE.
Provides examples of procedures for setting RF parameters like transmission and reception.
Offers notices and cautions for using the baseband function, particularly regarding transmission and address filters.
Describes the two types of interrupt functions: maskable and software interrupts.
Lists interrupt sources and their configurations, including reset sources and vector codes.
Lists registers related to interrupt functions, such as request flags, mask flags, and priority specification flags.
Explains operations related to interrupt servicing, including acknowledgment and multiple interrupt servicing.
Explains the standby function's purpose of reducing operating current and its three modes: HALT, STOP, and SNOOZE.
Lists registers that control standby functions, including subsystem clock control and oscillation stabilization registers.
Describes the operating statuses of HALT, STOP, and SNOOZE modes.
Explains the timing of internal reset signals generated by various sources like external reset, POR, and LVD.
Introduces the reset control flag register (RESF) used to store the source of the reset request.
Details the functions of the power-on-reset circuit, including generating internal reset signals at power on.
Shows the block diagram of the power-on-reset circuit.
Explains the timing of internal reset signal generation by the power-on-reset circuit and voltage detector.
Explains the functions of the voltage detector, including comparing supply voltage with detection voltage.
Shows the block diagram of the voltage detector.
Lists registers controlling the voltage detector, including voltage detection and level setting registers.
Describes the operation of the voltage detector in different modes (interrupt & reset, reset, interrupt).
Lists important cautions for using the voltage detector, covering operating current, conflicting operations, and noise countermeasures.
Provides an overview of safety functions for self-diagnosis and abnormality detection.
Lists registers used by safety functions, such as CRC control and parity error detection registers.
Explains the operation of safety functions like flash memory CRC, RAM parity error detection, and SFR guard.
Provides an overview of the regulator circuit for operating the device with a constant voltage.
Explains the functions of option bytes for setting user configurations like watchdog timer and LVD operation.
Shows the format of the user option byte, detailing settings for flash operation mode and oscillator frequency.
Describes the format of the on-chip debug option byte for controlling debug operation and security ID.
Details serial programming methods using a flash memory programmer or external device.
Explains pin connections required for flash memory programming.
Outlines the procedures for writing, erasing, and verifying flash memory.
Shows processing times for commands when using the PG-FP5 programmer.
Describes the self-programming function for rewriting flash memory via user programs.
Explains the security function to prohibit rewriting user programs and the relationship between erase/write commands and security.
Provides an overview of the data flash memory and its access methods.
Explains how to connect the E1 on-chip debugging emulator for serial communication.
Describes the on-chip debug operation control bit and security ID setting area.
Explains the need to secure memory space for debug functions to prevent user program interference.
Explains the function of the BCD correction circuit for obtaining add/subtract result as BCD code.
Lists the registers used by the BCD correction circuit.
Explains the basic operation of the BCD correction circuit, including addition and subtraction.
Defines conventions and symbols used in the operation list for instruction descriptions.
Provides a comprehensive list of instructions, their operands, bytes, clocks, and flag operations.
Lists the absolute maximum ratings for various parameters like supply voltage and input/output voltage.
Details the characteristics of X1 and XT1 oscillators, including frequency ranges and stabilization times.
Provides DC characteristics such as output current and input voltage levels.
Lists AC timing characteristics for various interfaces like CSI and UART.
Describes characteristics of peripheral functions like serial array units and I2C interfaces.
Details analog characteristics, including A/D converter and POR characteristics.
Covers RF transceiver characteristics, recommended operating conditions, and frequency sets.
Specifies RAM data retention characteristics.
Details characteristics related to flash memory programming.
Explains communication aspects with the dedicated flash memory programmer via UART.
Describes timing for switching between different flash memory programming modes.
Lists the major revisions made in the current edition of the manual.
Provides a history of revisions for previous editions of the manual.
