RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 571 of 920
Dec 22, 2016
(7) Transmit/receive status register 0 (BBTXRXST0)
This register stores the RF transmit/receive status.
It stores the CCA judge result in bit 0.
It stores the CRC judge result in bit 1. The CRC result corresponding to the save bank which is specified by
the receive data save bank select bit is read out when reading.
It stores the CSMA-CA judge result in bit 2.
The transmit/receive operation completion judge result bit is used to store the result of transmit/receive
operation sequence (CSMA-CA → Transmit → ACK receive → Retransmit → ACK receive, and so on)
judge upon
completion. The result is NG (no good) when the ACK receive cannot be performed even if the sequences
from the transmission of the number of setting times to the ACK receive are repeated.
The receive RAM bank 0 status bit and the receive RAM bank 1 status bit can be used as flags upon data
capture for the respective receive RAM banks 0 and 1.
1 is automatically set upon completion of the data receive. Later on, they are cleared to 0 by software after
reading the receive RAM data. Set 1 when no data is written because setting 0 enables writing. A receive
overrun interrupt occurs when data is received again under the status that 1 is set to these bits resulting in
the occurrence of write to each receive RAM.
It stores the pending bit data of the received ACK data in the receive pending bit upon completion of the
reception of only the ACK data.
The receive RAM bank pointer bit can be used to check the receive RAM bank after the completion of
receive. It indicates 1 after reset or initialization. This bit changes when the receive RAM bank is full or when
the frame
receive is complete.
The BBTXRXST0 register is set by the serial interface in 8-bit units.
Reset signal generation sets this register to 80H.
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