Renesas RL78/G1H

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RL78/G1H CHAPTER 18 RF TRANSCEIVER

R01UH0575EJ0120 Rev. 1.20 Page 572 of 920

Dec 22, 2016

Figure 18 - 13 Transmit/Receive Status Register 0 (BBTXRXST0) Format

Note Bits 0 to 3, 6, and 7 are Read Only.

Address:

0007H

After reset:

80H

R/W

Note

Symbol76543210

BBTXRXS

RCVRAMST RCVPEND RCVBANK1 RCVBANK0 TRNRCVSQC CSMACA CRC CCA

RCVRAMST Receive RAM bank pointer bit

0 Receive RAM bank 0

1 Receive RAM bank 1

RCVPEND Receive pending bit

0 No pending

1 Pending exists

RCVBANK1 Receive RAM bank 1 status bit

0 Receive enabled

1 Receive data exists

RCVBANK0 Receive RAM bank 0 status bit

0 Receive enabled

1 Receive data exists

TRNRCVSQC

Transmit/receive operation completion judge result bit

0OK

1NG

CSMACA CSMA-CA judge result bit

0OK

1NG

CRC CRC judge result bit

0OK

1NG

CCA CCA judge result bit

0 Channel clear

1 Channel busy

Main Page

Default Chapter7
- Table of Contents7
1 Outline19
- Features19
- Ordering Information22
- Pin Configuration (Top View)24
- Pin Identification25
- Block Diagram26
- Outline of Functions27
2 Connection between Mcu and Rf Transceiver29
- Connection Pins of MCU and RF Transceiver29
- Communication Interface between MCU and RF Transceiver30
- Initial Settings of Unused Internal Pins of MCU31
- Base Operation Clock of RF Unit32
- Power Configuration33
- Peripheral Circuits'connection Diagram34
3 Pin Functions37
- Port Functions37
- Functions Other than Port Pins40
- Connection of Unused Pins41
- Pin Block Diagrams42
4 Cpu Architecture54
- Memory Space54
- Processor Registers66
5 Port Functions85
- Port Configuration86
- Registers Controlling Port Function91
- Port Function Operations103
- Register Settings When Using Alternate Function105
- Cautions When Using Port Function113
  - Cautions on 1-Bit Manipulation Instruction for Port Register N (Pn)113
  - Notes on Specifying the Pin Settings114
6 Clock Generator115
- Functions of Clock Generator115
- Configuration of Clock Generator117
- Registers Controlling Clock Generator119
- System Clock Oscillator135
- Clock Generator Operation140
- Controlling Clock142
7 Timer Array Unit157
- Functions of Timer Array Unit158
- Configuration of Timer Array Unit160
  - Timer Count Register Mn (Tcrmn)164
  - Timer Data Register Mn (Tdrmn)166
- Registers Controlling Timer Array Unit167
- Basic Rules of Timer Array Unit190
  - Basic Rules of Simultaneous Channel Operation Function190
  - Basic Rules of 8-Bit Timer Operation Function (Channels 1 and 3 Only)192
- Operation of Counter193
- Channel Output (Tomn Pin) Control201
- Timer Input (Timn) Control210
- Independent Channel Operation Function of Timer Array Unit212
- Simultaneous Channel Operation Function of Timer Array Unit233
  - Operation as PWM Function233
- Cautions When Using Timer Array Unit240
  - Cautions When Using Timer Output240
8 Timer Rj241
- Functions of Timer RJ241
- Configuration of Timer RJ242
- Registers Controlling Timer RJ243
- Timer RJ Operation249
- Cautions for Timer RJ252
9 Real-Time Clock254
- Functions of Real-Time Clock254
- Configuration of Real-Time Clock254
- Registers Controlling Real-Time Clock256
- Real-Time Clock Operation271
10 Bit Interval Timer279
- Functions of 12-Bit Interval Timer279
- Configuration of 12-Bit Interval Timer279
- Registers Controlling 12-Bit Interval Timer280
- 12-Bit Interval Timer Operation283
  - 12-Bit Interval Timer Operation Timing283
  - Start of Count Operation and Re-Enter to HALT/STOP Mode after Returned from HALT/STOP Mode284
11 Clock Output/Buzzer Output Controller285
- Functions of Clock Output/Buzzer Output Controller285
- Configuration of Clock Output/Buzzer Output Controller287
- Registers Controlling Clock Output/Buzzer Output Controller287
  - Clock Output Select Registers N (Cksn)287
  - Registers Controlling Port Functions of Pins to be Used for Clock or Buzzer Output289
- Operations of Clock Output/Buzzer Output Controller290
  - Operation as Output Pin290
- Cautions of Clock Output/Buzzer Output Controller290
12 Watchdog Timer291
- Functions of Watchdog Timer291
- Configuration of Watchdog Timer292
- Register Controlling Watchdog Timer293
  - Watchdog Timer Enable Register (WDTE)293
- Operation of Watchdog Timer294
13 A/D Converter298
- Function of A/D Converter298
- Configuration of A/D Converter301
- Registers Controlling A/D Converter303
- A/D Converter Conversion Operations321
- Input Voltage and Conversion Results323
- A/D Converter Operation Modes324
- A/D Converter Setup Flowchart330
- SNOOZE Mode Function334
- Cautions for A/D Converter337
14 Serial Array Unit341
- Functions of Serial Array Unit342
  - 3-Wire Serial I/O (Csip)342
  - UART (Uartq)343
- Configuration of Serial Array Unit344
  - Shift Register347
  - Lower 8 Bits of the Serial Data Register Mn (Sdrmn)347
- Registers Controlling Serial Array Unit349
- Operation Stop Mode370
  - Stopping the Operation by Units370
  - Stopping the Operation by Channels371
- Operation of 3-Wire Serial I/O (Csip) Communication372
- Operation of UART (Uartq) Communication423
15 Serial Interface Iica445
- Functions of Serial Interface IICA445
- Configuration of Serial Interface IICA448
- Registers Controlling Serial Interface IICA451
- I 2 C Bus Mode Functions465
  - Pin Configuration465
  - Setting Transfer Clock by Using Iicwln and Iicwhn Registers466
- I 2 C Bus Definitions and Control Methods468
- Timing Charts517
16 Data Transfer Controller (Dtc)532
- Functions of DTC532
- Configuration of DTC534
- Registers Controlling DTC535
- DTC Operation547
- Cautions for DTC553
17 Event Link Controller (Elc)558
- Functions of ELC558
- Configuration of ELC558
- Registers Controlling ELC559
  - ELC Operation561
18 Rf Transceiver562
- RF Transceiver Overview563
- Pin Functions564
- Configuration of RF Transceiver566
- Baseband Function569
- Serial Interface Only for Internal Communication669
- RF Mode673
- Example of Procedure for Setting681
- Notice for Using Baseband Function722
  - Notice about Transmission722
  - Cautions on First and Second Address Filter Match Monitor Bits722
19 Interrupt Functions723
- Interrupt Function Types723
- Interrupt Sources and Configuration723
- Registers Controlling Interrupt Functions727
- Interrupt Servicing Operations739
20 Standby Function749
- Registers Controlling Standby Function750
21 Reset Function764
- Timing of Reset Operation766
- Register for Confirming Reset Source770
22 Power-On-Reset Circuit773
- Configuration of Power-On-Reset Circuit774
23 Voltage Detector778
- Configuration of Voltage Detector779
  - Voltage Detection Register (LVIM)780
  - Voltage Detection Level Register (LVIS)781
- Operation of Voltage Detector782
24 Safety Functions793
- Registers Used by Safety Functions794
25 Regulator814
26 Option Byte815
- On-Chip Debug Option Byte (000C3H/ 010C3H)816
- Format of User Option Byte817
- Format of On-Chip Debug Option Byte823
- Flash Memory824
27 Flash Memory825
- Serial Programming Using Flash Memory Programmer825
  - Programming Environment826
- Connection of Pins on Board828
  - Port Pins829
- Programming Method830
- Processing Time for each Command When PG-FP5 Is in Use (Reference Value)835
- Self-Programming836
- Security Settings841
- Data Flash843
  - Register Controlling Data Flash Memory844
  - Procedure for Accessing Data Flash Memory845
28 On-Chip Debug Function846
- On-Chip Debug Security ID847
29 Bcd Correction Circuit849
- BCD Correction Circuit Operation850
30 Instruction Set852
- Conventions Used in Operation List853
  - Description of Operation Column854
  - Description of Flag Operation Column855
- Operation List856
31 Electrical Specifications874
- Absolute Maximum Ratings875
- Oscillator Characteristics877
- Peripheral Functions Characteristics893
- Serial Interface IICA909
- Analog Characteristics912
- DC Characteristics918
- AC Characteristics922
- RAM Data Retention Characteristics925
- Timing for Switching Flash Memory Programming Modes926
32 Package Drawing927
Appendix A Revision History928
- A.2 Revision History of Preceding Editions930

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