Renesas RL78/G1H

RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 574 of 920
Dec 22, 2016
(9) Transmit/receive mode register 3 (BBTXRXMODE3)
This register sets the various types of the RF transmit/receive mode.
The address filter enable bit can be used to enable the address filter upon receiving.
When this bit is set to “1”, address filter on first address side is enabled.
The PAN coordinator bit can be used to set whether the PAN coordinator is set as one of the address filter
conditions on first address side.
Reception is enabled by receive enable bit. The bit must be set to 1 in receive operation.
Receive level filter enable bit can be used to suspend reception and enable receive level filter interrupt
when a communication error occurs such as no signal state during frame reception. The state enters to
waiting reception again after the suspension through IDLE automatically. Receive completion interrupt does
not occur because the suspension is done during frame reception. Destroy the receive frame when receive
level filter interrupt occurs. An overwrite enable processing might be required depending on the destroyed
timing. Then changing to enable reception of receive bank 0, 1 status bits for corresponding bank, or
enabling receive RAM overwrite enable bit is required. Set this bit and receive level filter interrupt enable bit
to “1” in initialization.
The receive data save bank select bit specifies the save bank to access the read of the receive-related data
(other than the receive RAM).
The receive RAM overwrite enable bit can control the overwrite to the receive RAM. However, the receive
data is not overwritten when write access to each receive RAM occurs when the above bit is 0 and receive
RAM bank status bit is 1. The receive data is overwritten when write access to each receive RAM occurs
when the receive RAM overwrite enable bit is 1 even if the receive RAM bank status bit is 1.
The address filter address extension bit can extend the first address and the second address in two ways.
The address filter general-purpose mode bit can set the address filter operation to the general-purpose
mode.
The BBTXRXMODE3 register is set by the serial interface in 8-bit units.
Reset signal generation clears this register to 00H.