RL78/G1H CHAPTER 18 RF TRANSCEIVER
R01UH0575EJ0120 Rev. 1.20 Page 596 of 920
Dec 22, 2016
(28) Baseband interrupt source register 2 (BBINTREQ2)
This register is used to indicate the baseband interrupt source.
This register indicates that “1” is set to the interrupt source corresponding to each interrupt occurrence
timing so that there is an interrupt request. When reading this register, only the bit from which 1 is read is
cleared to 0. Note that perform the dummy read when you clear the bit because writing is disabled.
The BBINTREQ2 register consists of 8 bits and can be accessed (serial interface communication) in 8 bit
unit.
Note
Reset signal generation clears this register to 00H.
Note When reading this register, read 3 bytes of the baseband interrupt source registers 0 to 2
(BBINTREQ0 to BBINTREQ2) continuously (leave SEN internal pin low level).
Figure 18 - 37 Baseband Interrupt Source Register 2 (BBINTREQ2) Format
Caution Bit 0 to 3 , 7 are X (undefined).
Address:
0038H
After reset: 00H R
Symbol76543210
BBINTREQ2
X
BYTERCVINTREQ
FLINTREQ
RCVCUNTINTREQ
XXXX
BYTERCVINTREQ
Byte receive completion interrupt source bit
0 No request
1 Request exists
FLINTREQ Frame length interrupt source bit
0 No request
1 Request exists
RCVCUNTINTREQ
Number of received byte interrupt source bit
0 No request
1 Request exists
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