RL78/G1H CHAPTER 20 STANDBY FUNCTION
R01UH0575EJ0120 Rev. 1.20 Page 742 of 920
Dec 22, 2016
(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 20 - 6 STOP Mode Release by Reset
(1) When high-speed on-chip oscillator clock is used as CPU clock
(2) When high-speed system clock is used as CPU clock
Note For the reset processing time, see CHAPTER 21 RESET FUNCTION.
Status of CPU
STOP instruction
Wait for oscillation accuracy stabilization
Oscillates Oscillation stopped
Oscillation
stopped
Oscillates
Normal operation
(high-speed on-chip
oscillator clock)
STOP mode
Reset
period
Normal operation
(high-speed on-chip
oscillator clock)
High-speed on-chip
oscillator clock
Reset signal
Note
Oscillation stabilization time
(Check by using OSTC register)
STOP instruction
Oscillates
High-speed system clock
(X1 oscillation)
Status of CPU
Reset signal
Oscillation stopped
Oscillation
stopped
Oscillation
stopped
Oscillates
Normal operation
(high-speed
system clock)
STOP mode
Reset
period
Normal operation
(high-speed on-chip
oscillator clock)
Starting X1 oscillation is specified by software.
Note
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