RL78/G1H CHAPTER 20 STANDBY FUNCTION
R01UH0575EJ0120 Rev. 1.20 Page 741 of 920
Dec 22, 2016
Figure 20 - 5 STOP Mode Release by Interrupt Request Generation (2/2)
(2) When high-speed system clock (X1 oscillation) is used as CPU clock
Note 1. For details of the standby release signal, see Figure 19 - 1 Basic Configuration of Interrupt Function.
Note 2. STOP mode release time
Supply of the clock is stopped: 18 μs to “whichever is longer 65 μs or the oscillation stabilization time (set by OSTS)”
Wait:
•When vectored interrupt servicing is carried out: 10 to 11 clocks
•When vectored interrupt servicing is not carried out: 4 to 5 clocks
(3) When high-speed system clock (external clock input) is used as CPU clock
Note 1. For details of the standby release signal, see Figure 19 - 1 Basic Configuration of Interrupt Function.
Note 2.
STOP mode release time
Supply of the clock is stopped: 18 to 65
μ
s
Wait:
•When vectored interrupt servicing is carried out: 7 clocks
•When vectored interrupt servicing is not carried out: 1 clock
Caution To reduce the oscillation stabilization time after release from the STOP mode while CPU operates based on
the high-speed system clock (X1 oscillation), switch the clock to the high-speed on-chip oscillator clock
temporarily before executing the STOP instruction.
Remark 1.
The clock supply stop time varies depending on the temperature conditions and STOP mode period.
Remark 2. The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
STOP
instruction
Oscillates
Interrupt
request
High-speed
system clock
(X1 oscillation)
Status of CPU
Standby release signal
Note 1
OscillatesOscillation stopped
Normal operation
(high-speed
system clock)
STOP mode
Supply of the
clock is stopped
Normal operation
(high-speed
system clock)
Wait
STOP mode release time
Note 2
STOP
instruction
Interrupt
request
High-speed system clock
(external clock input)
Status of CPU
Standby release signal
Note 1
Oscillates OscillatesOscillation stopped
Normal operation
(high-speed
system clock)
STOP mode
Normal operation
(high-speed system clock)
Wait
Supply of the
clock is stopped
STOP mode release time
Note 2
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