RL78/G1H CHAPTER 26 OPTION BYTE
R01UH0575EJ0120 Rev. 1.20 Page 800 of 920
Dec 22, 2016
Note 3. When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to
WDTE) must proceed outside the corresponding period from among those listed below, over which clearing
of the counter is prohibited (for example, confirming that the interval timer interrupt request flag (WDTIIF) of
the watchdog timer is set).
Remark fIL: Low-speed on-chip oscillator clock frequency
Figure 26 - 2 Format of User Option Byte (000C1H/010C1H) (1/4)
• LVD setting (interrupt & reset mode)
Note Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is
replaced by 010C1H.
Caution Be sure to set bit 4 to “1”.
Remark 1.
For details on the LVD circuit, see CHAPTER 23 VOLTAGE DETECTOR.
Remark 2. The detection voltage is a typical value. For details, see 31.6.3 LVD characteristics.
WDCS2 WDCS1 WDCS0
Watchdog timer overflow time
(f
IL = 17.25 kHz (MAX.))
Period over which clearing the
counter is prohibited when the
window open period is set to 75%
000
2
6
/fIL (3.71 ms)
1.85 to 2.51 ms
001
2
7
/fIL (7.42 ms)
3.71 to 5.02 ms
010
2
8
/fIL (14.84 ms)
7.42 to 10.04 ms
011
2
9
/fIL (29.68 ms)
14.84 to 20.08 ms
100
2
11
/fIL (118.72 ms)
56.36 to 80.32 ms
101
2
13
/fIL (474.90 ms)
237.44 to 321.26 ms
110
2
14
/fIL (949.80 ms)
474.89 to 642.51 ms
111
2
16
/fIL (3799.19 ms)
1899.59 to 2570.04 ms
Address: 000C1H/010C1H
Note
76543210
VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0
Detection Voltage Option Byte Setting Value
V
LVDH VLVDL
VPOC2 VPOC1 VPOC0 LVIS1 LVIS0
Mode setting
Rising edge Falling edge Falling edge LVIMDS1 LVIMDS0
1.98 V 1.94 V 1.84 V 0 0 1 1 0 1 0
2.09 V 2.04 V 0 1
3.13 V 3.06 V 0 0
2.61 V 2.55 V 2.45 V 1 0 1 0
2.71 V 2.65 V 0 1
2.92 V 2.86 V 2.75 V 1 1 1 0
3.02 V 2.96 V 0 1
— Settings other than the above are prohibited
To Next Page
Loading...
Need help?
General
