Renesas RL78/G1H User Manual

RL78/G1H CHAPTER 30 INSTRUCTION SET
R01UH0575EJ0120 Rev. 1.20 Page 840 of 920
Dec 22, 2016
Note 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no
data is accessed.
Note 2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is accessed by
an 8-bit instruction.
Note 3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the
internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Table 30 - 7 Operation List (3/18)
Instruction
Group
Mnemonic Operands Bytes
Clocks
Clocks
Flag
Note 1 Note 2
ZACCY
8-bit data
transfer
MOV A, [HL+B]
214
A
←
(HL + B)
[HL+B], A
21—
(HL + B)
←
A
A, ES:[HL+B]
325
A
←
((ES, HL) + B)
ES:[HL+B], A
32—
((ES, HL) + B)
←
A
A, [HL+C]
214
A
←
(HL + C)
[HL+C], A
21—
(HL + C)
←
A
A, ES:[HL+C]
325
A
←
((ES, HL) + C)
ES:[HL+C], A
32—
((ES, HL) + C)
←
A
X, !addr16
314
X
←
(addr16)
X, ES:!addr16
425
X
←
(ES, addr16)
X, saddr
21—
X
←
(saddr)
B, !addr16
314
B
←
(addr16)
B, ES:!addr16
425
B
←
(ES, addr16)
B, saddr
21—
B
←
(saddr)
C, !addr16
314
C
←
(addr16)
C, ES:!addr16
425
C
←
(ES, addr16)
C, saddr
21—
C
←
(saddr)
ES, saddr
31—
ES
←
(saddr)
XCH
A, r
Note 3
1 (r = X)
2 (other
than r = X)
1—
A
←→
r
A, !addr16
42—
A
←→
(addr16)
A, ES:!addr16
53—
A
←→
(ES, addr16)
A, saddr
32—
A
←→
(saddr)
A, sfr
32—
A
←→
sfr
A, [DE]
22—
A
←→
(DE)
A, ES:[DE]
33—
A
←→
(ES, DE)
A, [HL]
22—
A
←→
(HL)
A, ES:[HL]
33—
A
←→
(ES, HL)
A, [DE+byte]
32—
A
←→
(DE + byte)
A, ES:[DE+byte]
43—
A
←→
((ES, DE) + byte)
A, [HL+byte]
32—
A
←→
(HL + byte)
A, ES:[HL+byte]
43—
A
←→
((ES, HL) + byte)

Renesas RL78/G1H Specifications

General

Brand	Renesas
Model	RL78/G1H
Category	Microcontrollers
Language	English