RL78/G1H CHAPTER 30 INSTRUCTION SET
R01UH0575EJ0120 Rev. 1.20 Page 850 of 920
Dec 22, 2016
Note 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no
data is accessed.
Note 2. Number of CPU clocks (f
CLK) when the code flash memory is accessed, or when the data flash memory is accessed by
an 8-bit instruction.
Remark 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the
internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Remark 2. cnt indicates the bit shift count.
Table 30 - 17 Operation List (13/18)
Instruction
Group
Mnemonic Operands Bytes
Clocks
Clocks
Flag
Note 1 Note 2
ZACCY
Increment/
decrement
INC r
11—
r
←
r + 1
××
!addr16
32—
(addr16)
←
(addr16) + 1
××
ES:!addr16
43—
(ES, addr16)
←
(ES, addr16) + 1
××
saddr
22—
(saddr)
←
(saddr) + 1
××
[HL+byte]
32—
(HL + byte)
←
(HL + byte) + 1
××
ES: [HL+byte]
43—
((ES:HL) + byte)
←
((ES:HL) + byte) + 1
××
DEC r
11—
r
←
r - 1
××
!addr16
32—
(addr16)
←
(addr16) - 1
××
ES:!addr16
43—
(ES, addr16)
←
(ES, addr16) - 1
××
saddr
22—
(saddr)
←
(saddr) - 1
××
[HL+byte]
32—
(HL + byte)
←
(HL + byte) - 1
××
ES: [HL+byte]
43—
((ES:HL) + byte)
←
((ES:HL) + byte) - 1
××
INCW rp
11—
rp
←
rp + 1
!addr16
32—
(addr16)
←
(addr16) + 1
ES:!addr16
43—
(ES, addr16)
←
(ES, addr16) + 1
saddrp
22—
(saddrp)
←
(saddrp) + 1
[HL+byte]
32—
(HL + byte)
←
(HL + byte) + 1
ES: [HL+byte]
43—
((ES:HL) + byte)
←
((ES:HL) + byte) + 1
DECW rp
11—
rp
←
rp - 1
!addr16
32—
(addr16)
←
(addr16) - 1
ES:!addr16
43—
(ES, addr16)
←
(ES, addr16) - 1
saddrp
22—
(saddrp)
←
(saddrp) - 1
[HL+byte]
32—
(HL + byte)
←
(HL + byte) - 1
ES: [HL+byte]
43—
((ES:HL) + byte)
←
((ES:HL) + byte) - 1
Shift SHR A, cnt
21—
(CY
←
A
0, Am - 1
←
A
m, A7
←
0)
× cnt
×
SHRW AX, cnt
21—
(CY
←
AX
0, AXm - 1
←
AX
m, AX15
←
0)
× cnt
×
SHL A, cnt
21—
(CY
←
A
7, Am
←
A
m - 1, A0
←
0)
× cnt
×
B, cnt
21—
(CY
←
B
7, Bm
←
B
m - 1, B0
←
0)
× cnt
×
C, cnt
21—
(CY
←
C
7, Cm
←
C
m - 1, C0
←
0)
× cnt
×
SHLW AX, cnt
21—
(CY
←
AX
15, AXm
←
AX
m - 1, AX0
←
0)
× cnt
×
BC, cnt
21—
(CY
←
BC
15, BCm
←
BC
m - 1, BC0
←
0)
× cnt
×
SAR A, cnt
21—
(CY
←
A
0, Am - 1
←
A
m, A7
←
A
7) × cnt
×
SARW AX, cnt
21—
(CY
←
AX
0, AXm - 1
←
AX
m, AX15
←
AX
15) × cnt
×
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