6241A/6242 DC Voltage Current Source/Monitor Operation Manual
6.5 Status Register Structure
6-13
Common conditions on which the Status Byte Register is cleared.
• Every bit is cleared when the power is turned ON.
• *CLS clears every bit except MAV which is not cleared if data exists in the output buffer.
• All the bits in DSB, MAV, and ESB are cleared
• Not cleared even if read by *STB?.
Conditions on which the Service Request Enable Register is cleared.
• Power is turned ON.
• *SRE0 command is executed.
Table 6-3 Status Byte Register (STB)
bit Name Description
0 Not used Always set to 0
1 Not used Always set to 0
2 Not used Always set to 0
3DSB
Device Event Status
ON: 1 is set when any of the DESR incidents occur and 1 is set, if the correspond-
ing DESER bit is also 1.
OFF: 0 is set when DESR is cleared by reading (DSR?).
4MAV
Message Available
ON: 1 is set when output data is entered in the output buffer.
OFF: 0 is set when the output buffer is read and becomes empty.
5ESB
Standard Event Status
ON: 1 is set when any of the SESR incidents occur and 1 is set, if the correspond-
ing SESER bit is also 1.
OFF: 0 is set when SESR is cleared by reading (*ESR?).
6MSS
Master Summary
ON: 1 is set when any of the STB incidents occur and 1 is set, if the correspond-
ing SRER bit is 1.
RQS
Request Service
ON: 1 is set when MSS is set to 1, and SRQ is generated.
OFF: When STB is read by the Serial poll.
7 Not used Always set to 0
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