6241A/6242 DC Voltage Current Source/Monitor Operation Manual
6.5 Status Register Structure
6-14
4. Standard Event Status Register
Table 6-4 below shows the functions assigned to the Standard Event Status Register.
Common conditions on which the Standard Event Status Register is cleared.
• Every bit is cleared when the power is turned ON.
• *CLS clears every bit.
• Every bit is cleared when read by *ESR?.
Conditions on which the Standard Event Status Enable Register is cleared.
• Power is turned ON.
• *ESE0 command is executed.
Table 6-4 Standard Event Status Register (ESR)
bit Name Description
0OPC
Operation Complete
ON: When all operation is completed after receiving the *OPC command, bit 0 is
set to 1.
1 Not used Always set to 0
2 Not used Always set to 0
3 DDE
Device Dependent
Error
ON: 1 is set when an error related to the hardware occurs.
4EXE
Execution Error
ON: 1 is set when a received command is not currently executable.
1 is set when incorrect data is entered in a command parameter.
5CME
Command Error
ON: 1 is set when the received command is incorrectly spelled.
6 Not used Always set to 0
7PON
Power On
ON: 1 is set when the power is turned OFF and ON.
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