Chapter 4 INTERFACE SETTINGS
121
[3] MODE2 (Quad Link) (screen horizontally split into 2)
Using channels 1 and 2, the top half of the image is output in the even and odd numbers; similarly, using channels 3
and 4, the bottom half of the image is output in the even and odd numbers.
Given here as an example of the resolution is 4096 × 2048, the dot clock frequency is 592 MHz with 10bits output.
CLK
148MHz
1CH
2CH
3CH
4CH
・・・
L0~L1079
L0~L1079
L1080~L2159
L1080~L2159
D 4088 D 4090 D 4092 D 4094
[9:0] [9:0] [9:0] [9:0]
D 0
[9:0]
D 2 D 4 D 6
・・・
[9:0] [9:0] [9:0]
D 4089
[9:0]
D 4091 D 4093 D 4095
[9:0] [9:0] [9:0]
[9:0]
・・・
[9:0] [9:0] [9:0]
D 1 D 3 D 5 D 7
D 4088 D 4090 D 4092 D 4094
[9:0] [9:0] [9:0] [9:0]
D 0
[9:0]
D 2 D 4 D 6
・・・
[9:0] [9:0] [9:0]
D 4089
[9:0]
D 4091 D 4093 D 4095
[9:0] [9:0] [9:0]
[9:0]
・・・
[9:0] [9:0] [9:0]
D 1 D 3 D 5 D 7
1CH 2CH 3CH 4CH