122
[4] MODE3 (Quad Link) (screen vertically split into 2)
Using channels 1 and 2, the left half of the image is output in the even and odd numbers; similarly, using channels 3
and 4, the right half of the image is output in the even and odd numbers.
Given here as an example of the resolution is 4096 × 2048, the dot clock frequency is 592 MHz with the 10 bits
output.
CLK
148MHz
1CH
2CH
3CH
4CH
・・・
D 2040 D 2042 D 2044 D 2046
[9:0] [9:0] [9:0] [9:0]
D 0
[9:0]
D 2 D 4 D 6
・・・
[9:0] [9:0] [9:0]
D 2041
[9:0]
D 2043 D 2045 D 2047
[9:0] [9:0] [9:0]
[9:0]
・・・
[9:0] [9:0] [9:0]
D 1 D 3 D 5 D 7
D 4088 D 4090 D 4092 D 4094
[9:0] [9:0] [9:0] [9:0]
D 2048
[9:0]
D 2050 D 2052 D 2054
・・・
[9:0] [9:0] [9:0]
D 4089
[9:0]
D 4091 D 4093 D 4095
[9:0] [9:0] [9:0][9:0]
・・・
[9:0] [9:0] [9:0]
D 2049 D 2051 D 2053 D 2055
1CH 2CH 3CH 4CH