222
[2] MODE1 (8 Lane) - 4Split
The image is split horizontally into four parts and assigned in sequence from the left using lanes 1 and 2, lanes 3 and
4, lanes 5 and 6 and lanes 7 and 8.
Given here as an example where the resolution is 4096 × 2048, the dot clock frequency is 592 MHz and the output
bit depth is 10 bits.
・・・
CLK
74MHz
D 1020
D 1021
D 1022
D 1023
[9:0] [9:0] [9:0] [9:0]
D 4
[9:0]
D 5
D 6
D 7
・・・
[9:0] [9:0] [9:0]
D 2044
[9:0]
D 2045
D 2046
D 2047
[9:0] [9:0] [9:0]
[9:0]
・・・
[9:0] [9:0] [9:0]
D 1028
D 1029
D 1030
D 1031
D 4092
[9:0]
D 4093
D 4094
D 4095
[9:0]
[9:0]
[9:0]
[9:0]
・・・
[9:0]
[9:0]
[9:0]
D 3076
D 3077
D 3078
D 3079
D 3068
[9:0]
D 3069
D 3070
D 3071
[9:0] [9:0] [9:0]
[9:0]
・・・
[9:0] [9:0] [9:0]
D 2052
D 2053
D 2054
D 2055
・・・
・・・
・・・
・・・
D 4088
[9:0]
D 4089
D 4090
D 4091
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0] [9:0] [9:0] [9:0][9:0] [9:0] [9:0] [9:0]
[9:0] [9:0] [9:0] [9:0][9:0] [9:0] [9:0] [9:0]
[9:0] [9:0] [9:0] [9:0][9:0] [9:0] [9:0] [9:0]
D 3064
D 3065
D 3066
D 3067
D 2040
D 2041
D 2042
D 2043
D 1016
D 1017
D 1018
D 1019
D 1024
D 1025
D 1026
D 1027
D 0
D 1
D 2
D 3
D 3072
D 3073
D 3074
D 3075
D 2048
D 2049
D 2050
D 2051
L0~L2159
L0~L2159
L0~L2159
L0~L2159
L0~L2159
L0~L2159
L0~L2159
L0~L2159
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Lane 1 Lane 2 Lane 3 Lane4 Lane 5 Lane 6 Lane 7 Lane 8
Lane 5-6 Lane 7-8Lane 1-2 Lane 3-4