Intel Xeon User Manual

Design Guide 201
Schematic Checklist
Power Management
THRM# • Connect to temperature Sensor. Pull-up if
not used with an 8.2 k
Ω ± 5% pull-up resistor
to VCC_3.3.
• Input to ICH3-S cannot float.
THRM# polarity bit defaults
THRM# to active low, so pull up
to VCC_3.3.
SLP_S3#
SLP_S5#
• No pull-up/down resistors needed. Signals
driven by ICH3-S.
• Signals driven by ICH3-S.
PWROK • This signal should be connected to power
monitoring logic, and should go high no
sooner than 10 ms after both VCC_3.3 and
VCC_1.8 have reached their nominal
voltages.
• Use external weak pull-down (see
Section 9.6.8).
• Timing Requirement.
PWRBTN# • No extra pull-up resistors. • This signal has an integrated
pull-up of 18 k
Ω – 42 kΩ.
RI# • RI# does not have an internal pull-up.
Recommend an 8.2 k
Ω ± 5% pull-up resistor
to resume well.
• If this signal is enabled as a
wake event, it is important to
keep this signal powered during
the power loss event. If this
signal goes low (active), when
power returns the RI_STS bit
will be set, and the system will
interpret that as a wake event.
RSMRST# • This signal should be connected to power
monitoring logic, and should go high no
sooner than 10 ms after both VCCSUS3.3
and VCCSUS1.8 have reached their
nominal voltages. Can be tied to LAN_RST#
on server Platforms.
• Use external weak pull-down (see
Section 9.6.8).
• Timing Requirement.
SUS_STAT# • Disconnect from ICH3-S and leave not
connected. Use 8.2 k
Ω pull-up to VCC_3.3
for remaining devices on LPC bus.
DPRSLPVR • Leave as no connect. • Integrated pull-down.
Table 13-3. Intel
®
ICH3-S Schematic Checklist (Sheet 6 of 8)
Checklist Items Recommendations Comments

Intel Xeon Specifications

General

Brand	Intel
Model	Xeon
Category	Processor
Language	English