dsPIC30F Family Reference Manual
DS70052C-page 5-12 © 2004 Microchip Technology Inc.
5.4.2.3 Loading Write Latches
The following is a sequence of instructions that can be used to load the 768-bits of write latches
(32 instruction words). 32 TBLWTL and 32 TBLWTH instructions are needed to load the write
latches selected by the table pointer.
The TBLPAG register is loaded with the 8 MSbits of the program memory address. The user
does not need to write the NVMADRU:NVMADR register-pair for a Flash programming opera-
tion. The 24-bits of the program memory address are automatically captured into the
NVMADRU:NVMADR register-pair when each table write instruction is executed. The program
memory must be programmed at an ‘even’ 32 instruction word address boundary. In effect, the
6 LSbits of the value captured in the NVMADR register are not used during the programming
operation.
The row of 32 instruction words do not necessarily have to be written in sequential order. The
6 LSbits of the table write address determine which of the latches will be written. However, all 32
instruction words should be written for each programming cycle to overwrite old data.
; Set up a pointer to the first program memory location to be written.
MOV #tblpage(PROG_ADDR),W0
MOV W0
,
TBLPAG
MOV #tbloffset(PROG_ADDR),W0
; Perform the TBLWT instructions to write the latches
; W0 is incremented in the TBLWTH instruction to point to the
; next instruction location.
MOV #LOW_WORD_0,W2
MOV #HIGH_BYTE_0,W3
TBLWTL W2
,
[W0]
TBLWTH W3
,
[W0++] ; 1st_program_word
MOV #LOW_WORD_1,W2
MOV #HIGH_BYTE_1,W3
TBLWTL W2
,
[W0]
TBLWTH W3,[W0++] ; 2nd_program_word
MOV #LOW_WORD_2,W2
MOV #HIGH_BYTE_2,W3
TBLWTL W2
,
[W0]
TBLWTH W3
,
[W0++] ; 3rd_program_word
MOV #LOW_WORD_3,W2
MOV #HIGH_BYTE_3,W3
TBLWTL W2
,
[W0]
TBLWTH W3,[W0++] ; 4th_program_word
........
........
MOV #LOW_WORD_31,W2
MOV #HIGH_BYTE_31,W3
TBLWTL W2
,
[W0]
TBLWTH W3,[W0++] ; 32nd_program_word
Note: The following code example is the ‘Load_Write_Latch’ code referred to in
subsequent examples.
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