Microchip Technology dsPIC30F - Page 113

© 2004 Microchip Technology Inc. DS70052C-page 5-17
Section 5. Flash and EEPROM Programming
Flash and EEPROM
Programming
5
5.5.4 Writing One Word of Data EEPROM Memory
Assuming the user has erased the EEPROM location to be programmed, use a table write
instruction to write one write latch. The TBLPAG register is loaded with the 8 MSBs of the
EEPROM address. The 16 LSBs of the EEPROM address are automatically captured into the
NVMADR register when the table write is executed. The LSB of the NVMADR register has no
effect on the programming operation. The NVMCON register is configured to program one word
of data EEPROM.
Setting the WR control bit (NVMCON<15>) initiates the programming operation. A special unlock
or key sequence should be written to the NVMKEY register before setting the WR control bit. The
unlock sequence needs to be executed in the exact order shown without interruption. Therefore,
interrupts should be disabled prior to writing the sequence.
; Setup a pointer to data EEPROM
MOV #tblpage(EE_ADDR),W0
MOV W0
,
TBLPAG
MOV #tbloffset(EE_ADDR),W0
; Write data value to holding latch
MOV EE_DATA,W1
TBLWTL W1
,
[ W0]
; NVMADR captures write address from the TBLWTL instruction.
; Setup NVMCON for programming one word to data EEPROM
MOV #0x4004,W0
MOV W0
,
NVMCON
; Disable interrupts while the KEY sequence is written
PUSH SR
MOV #0x00E0,W0
IOR SR
; Write the key sequence
MOV #0x55,W0
MOV W0,NVMKEY
MOV #0xAA,W0
MOV W0,NVMKEY
; Start the write cycle
BSET NVMCON,#WR
;Re-enable interrupts, if needed
POP SR