Microchip Technology dsPIC30F - Page 114

dsPIC30F Family Reference Manual
DS70052C-page 5-18 © 2004 Microchip Technology Inc.
5.5.5 Erasing One Row of Data EEPROM
The NVMCON register is configured to erase one row of EEPROM memory. The TABPAG and
NVMADR registers must point to the row to be erased. The data EEPROM must be erased at
even address boundaries. Therefore, the 5 LSBs of the NVMADR register will have no effect on
the row that is erased.
Setting the WR control bit (NVMCON<15>) initiates the erase. A special unlock or key sequence
should be written to the NVMKEY register before setting the WR control bit. The unlock sequence
needs to be executed in the exact order shown without interruption. Therefore, interrupts should
be disabled prior to writing the sequence.
; Set up a pointer to the EEPROM row to be erased.
MOV #tblpage(EE_ADDR),W0
MOV W0
,
TBLPAG
MOV #tbloffset(EE_ADDR),W0
MOV W0,NVMADR
; Setup NVMCON to erase one row of EEPROM
MOV #0x4045,W0
MOV W0
,
NVMCON
; Disable interrupts while the KEY sequence is written
PUSH SR
MOV #0x00E0,W0
IOR SR
; Write the KEY Sequence
MOV #0x55,W0
MOV W0,NVMKEY
MOV #0xAA,W0
MOV W0,NVMKEY
; Start the erase operation
BSET NVMCON,#WR
;Re-enable interrupts, if needed
POP SR