dsPIC30F Family Reference Manual
DS70053C-page 6-10 © 2004 Microchip Technology Inc.
6.2.4.2 Interrupt Nesting
Interrupts, by default, are nestable. Any ISR that is in progress may be interrupted by another
source of interrupt with a higher user assigned priority level. Interrupt nesting may be optionally
disabled by setting the NSTDIS control bit (INTCON1<15>). When the NSTDIS control bit is set,
all interrupts in progress will force the CPU priority to level 7 by setting IPL<2:0> = 111. This
action will effectively mask all other sources of interrupt until a RETFIE instruction is executed.
When interrupt nesting is disabled, the user assigned interrupt priority levels will have no effect,
except to resolve conflicts between simultaneous pending interrupts.
The IPL<2:0> bits become read only when interrupt nesting is disabled. This prevents the user
software from setting IPL<2:0> to a lower value, which would effectively re-enable interrupt
nesting.
6.2.5 Wake-up from Sleep and Idle
Any source of interrupt that is individually enabled, using its corresponding control bit in the IECx
registers, can wake-up the processor from Sleep or Idle mode. When the interrupt status flag for
a source is set and the interrupt source is enabled via the corresponding bit in the IEC Control
registers, a wake-up signal is sent to the dsPIC30F CPU. When the device wakes from Sleep or
Idle mode, one of two actions may occur:
1. If the interrupt priority level for that source is greater than the current CPU priority level,
then the processor will process the interrupt and branch to the ISR for the interrupt source.
2. If the user assigned interrupt priority level for the source is less than or equal the current
CPU priority level, then the processor will simply continue execution, starting with the
instruction immediately following the PWRSAV instruction that previously put the CPU in
Sleep or Idle mode.
6.2.6 A/D Converter External Conversion Request
The INT0 external interrupt request pin is shared with the A/D converter as an external
conversion request signal. The INT0 interrupt source has programmable edge polarity, which is
also available to the A/D converter external conversion request feature.
6.2.7 External Interrupt Support
The dsPIC30F supports up to 5 external interrupt pin sources (INT0-INT4). Each external
interrupt pin has edge detection circuitry to detect the interrupt event. The INTCON2 register has
five control bits (INT0EP-INT4EP) that select the polarity of the edge detection circuitry. Each
external interrupt pin may be programmed to interrupt the CPU on a rising edge or falling edge
event. See Register 6-4 for further details.
Note: User interrupt sources that are assigned to CPU priority level 0 cannot wake the
CPU from Sleep or Idle mode, because the interrupt source is effectively disabled.
To use an interrupt as a wake-up source, the CPU priority level for the interrupt must
be assigned to CPU priority level 1 or greater.
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