© 2004 Microchip Technology Inc. DS70061C-page 14-9
Section 14. Output Compare
Output
Compare
14
14.3.2 Dual Compare Match Mode
When control bits OCM<2:0> = ‘100’ or ‘101’ (OCxCON<2:0>), the selected output compare
channel is configured for one of two Dual Compare Match modes which are:
• Single Output Pulse mode
• Continuous Output Pulse mode
In the Dual Compare mode, the module uses both the OCxR and OCxRS registers for the
compare match events. The OCxR register is compared against the incrementing timer count,
TMRy, and the leading (rising) edge of the pulse is generated at the OCx pin, on a compare
match event. The OCxRS register is then compared to the same incrementing timer count,
TMRy, and the trailing (falling) edge of the pulse is generated at the OCx pin, on a compare
match event.
14.3.2.1 Dual Compare Mode: Single Output Pulse
To configure the Output Compare module for the Single Output Pulse mode, set control bits
OCM<2:0> = ‘100’. In addition, the compare time base must be selected and enabled. Once this
mode has been enabled, the output pin, OCx, will be driven low and remain low until a match
occurs between the time base and OCxR registers. Referring to Figure 14-6 and Figure 14-7,
there are some key timing events to note:
• The OCx pin is driven high one instruction clock after the compare match occurs between
the compare time base and OCxR register. The OCx pin will remain high until the next
match event occurs between the time base and the OCxRS register. At this time, the pin
will be driven low. The OCx pin will remain low until a mode change has been made, or the
module is disabled.
• The compare time base will count up to the value contained in the associated period
register and then reset to 0x0000 on the next instruction clock.
• If the time base period register contents are less than the OCxRS register contents, then no
falling edge of the pulse is generated. The OCx pin will remain high until
OCxRS <= PRy, or a mode change or Reset condition has occurred.
• The respective channel interrupt flag, OCxIF, is asserted 2 instruction clocks after the OCx
pin is driven low (falling edge of single pulse).
Figure 14-6 depicts the General Dual Compare mode generating a single output pulse.
Figure 14-7 depicts another timing example where OCxRS > PRy. In this example, no falling
edge of the pulse is generated since the compare time base resets before counting up to
0x4100.
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