Microchip Technology dsPIC30F - Page 293

© 2004 Microchip Technology Inc. DS70061C-page 14-11
Section 14. Output Compare
Output
Compare
14
14.3.2.2 Setup for Single Output Pulse Generation
When control bits OCM<2:0> (OCxCON<2:0>) are set to ‘100’, the selected output compare
channel initializes the OCx pin to the low state and generates a single output pulse.
To generate a single output pulse, the following steps are required (these steps assume timer
source is initially turned off, but this is not a requirement for the module operation):
1. Determine the instruction clock cycle time. Take into account the frequency of the external
clock to the timer source (if one is used) and the timer prescaler settings.
2. Calculate time to the rising edge of the output pulse relative to the TMRy start value
(0x0000).
3. Calculate the time to the falling edge of the pulse based on the desired pulse width and
the time to the rising edge of the pulse.
4. Write the values computed in steps 2 and 3 above into the compare register, OCxR, and
the secondary compare register, OCxRS, respectively.
5. Set timer period register, PRy, to value equal to or greater than value in OCxRS, the
secondary compare register.
6. Set OCM<2:0> = ‘100’ and the OCTSEL (OCxCON<3>) bit to the desired timer source.
The OCx pin state will now be driven low.
7. Set the TON (TyCON<15>) bit to ‘1’, which enables the compare time base to count.
8. Upon the first match between TMRy and OCxR, the OCx pin will be driven high.
9. When the incrementing timer, TMRy, matches the secondary compare register, OCxRS,
the second and trailing edge (high-to-low) of the pulse is driven onto the OCx pin. No
additional pulses are driven onto the OCx pin and it remains at low. As a result of the
second compare match event, the OCxIF interrupt flag bit set, which will result in an
interrupt if it is enabled, by setting the OCxIE bit. For further information on peripheral
interrupts, refer to Section 6. “Reset Interrupts”.
10. To initiate another single pulse output, change the timer and compare register settings, if
needed, and then issue a write to set OCM<2:0> (OCxCON<2:0>) bits to ‘100’. Disabling
and re-enabling of the timer and clearing the TMRy register are not required, but may be
advantageous for defining a pulse from a known event time boundary.
The output compare module does not have to be disabled after the falling edge of the output
pulse. Another pulse can be initiated by rewriting the value of the OCxCON register.