dsPIC30F Family Reference Manual
DS70061C-page 14-20 © 2004 Microchip Technology Inc.
14.3.3.3 PWM Duty Cycle
The PWM duty cycle is specified by writing to the OCxRS register. The OCxRS register can be
written to at any time, but the duty cycle value is not latched into OCxR until a match between
PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM
duty cycle and is essential for glitchless PWM operation. In the PWM mode, OCxR is a read only
register.
Some important boundary parameters of the PWM duty cycle include:
• If the duty cycle register, OCxR, is loaded with 0x0000, the OCx pin will remain low
(0% duty cycle).
• If OCxR is greater than PRy (timer period register), the pin will remain high (100% duty
cycle).
• If OCxR is equal to PRy, the OCx pin will be low for one time base count value and high for
all other count values.
See Figure 14-11 for PWM mode timing details. Table 14-3 and Table 14-4 show example PWM
frequencies and resolutions for a device operating at 10 and 30 MIPs, respectively.
Equation 14-2: Calculation for Maximum PWM Resolution
Example 14-5: PWM Period and Duty Cycle Calculation
(
)
Maximum PWM Resolution (bits) =
F
OSC
FPWM
log
10
log
10
(2)
bits
Desired PWM frequency is 52.08 kHz,
F
OSC = 10 MHz with x4 PLL (40 MHz device clock rate) (TCY = 4/FOSC))
Timer 2 prescale setting: 1:1
1/52.08 kHz = (PR2+1) • T
CY • (Timer 2 prescale value)
19.20 µs = (PR2+1) • 0.1 µ s • (1)
PR2 = 191
Find the maximum resolution of the duty cycle that can be used with a 48 kHz frequency
and a 40 MHz device clock rate.
1/52.08 kHz = 2
PWM RESOLUTION
• 1/40 MHz • 1
19.20 µs=2
PWM RESOLUTION
• 25 ns • 1
768 = 2
PWM RESOLUTION
log
10
(768) = (PWM Resolution) • log
10
(2)
PWM Resolution= 9.5 bits
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