© 2004 Microchip Technology Inc. DS70062C-page 15-7
Section 15. Motor Control PWM
Motor Control
PWM
15
Register 15-4: SEVTCMP: Special Event Compare Register
Register 15-5: PWMCON1: PWM Control Register 1
Upper Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTDIR SEVTCMP <14:8>
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP <7:0>
bit 7 bit 0
bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit
(1)
1 = A special event trigger will occur when the PWM time base is counting downwards.
0 = A special event trigger will occur when the PWM time base is counting upwards.
bit 14-0 SEVTCMP <14:0>: Special Event Compare Value bit
(2)
Note 1: SEVTDIR is compared with PTDIR (PTMR<15>) to generate the special event trigger.
2: SEVTCMP<14:0> is compared with PTMR<14:0> to generate the special event trigger.
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Upper Byte:
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — PMOD4 PMOD3 PMOD2 PMOD1
bit 15 bit 8
Lower Byte:
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PEN4H PEN3H PEN2H PEN1H PEN4L PEN3L PEN2L PEN1L
bit 7 bit 0
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 PMOD4:PMOD1: PWM I/O Pair Mode bits
1 = PWM I/O pin pair is in the independent output mode
0 = PWM I/O pin pair is in the complementary output mode
bit 7-4 PEN4H-PEN1H: PWMxH I/O Enable bits
(1)
1 = PWMxH pin is enabled for PWM output
0 = PWMxH pin disabled. I/O pin becomes general purpose I/O
bit 3-0 PEN4L-PEN1L: PWMxL I/O Enable bits
(1)
1 = PWMxL pin is enabled for PWM output
0 = PWMxL pin disabled. I/O pin becomes general purpose I/O
Note 1: Reset condition of the PENxH and PENxL bits depend on the value of the PWM/PIN device
configuration bit in the FBORPOR Device Configuration Register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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