Microchip Technology dsPIC30F - Page 318

dsPIC30F Family Reference Manual
DS70062C-page 15-8 © 2004 Microchip Technology Inc.
Register 15-6: PWMCON2: PWM Control Register 2
Upper Byte:
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — SEVOPS<3:0>
bit 15 bit 8
Lower Byte:
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — OSYNC UDIS
bit 7 bit 0
bit 15-12 Unimplemented: Read as ‘0’
bit 11-8 SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111 = 1:16 Postscale
•
•
0001 = 1:2 Postscale
0000 = 1:1 Postscale
bit 7-2 Unimplemented: Read as ‘0’
bit 1 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVDCON register are synchronized to the PWM time base
0 = Output overrides via the OVDCON register occur on next T
CY boundary
bit 0 UDIS: PWM Update Disable bit
1 = Updates from duty cycle and period buffer registers are disabled
0 = Updates from duty cycle and period buffer registers are enabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown