© 2004 Microchip Technology Inc. DS70062C-page 15-11
Section 15. Motor Control PWM
Motor Control
PWM
15
Register 15-9: FLTACON: Fault A Control Register
Upper Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L
bit 15 bit 8
Lower Byte:
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTAM
— — — FAEN4 FAEN3 FAEN2 FAEN1
bit 7 bit 0
bit 15-8 FAOV4H-FAOV1L: Fault Input A PWM Override Value bits
1 = The PWM output pin is driven ACTIVE on an external fault input event
0 = The PWM output pin is driven INACTIVE on an external fault input event
bit 7 FLTAM: Fault A Mode bit
1 = The Fault A input pin functions in the cycle-by-cycle mode
0 = The Fault A input pin latches all control pins to the programmed states in FLTACON<15:8>
bit 6-4 Unimplemented: Read as ‘0’
bit 3 FAEN4: Fault Input A Enable bit
1 = PWM4H/PWM4L pin pair is controlled by Fault Input A
0 = PWM4H/PWM4L pin pair is not controlled by Fault Input A
bit 2 FAEN3: Fault Input A Enable bit
1 = PWM3H/PWM3L pin pair is controlled by Fault Input A
0 = PWM3H/PWM3L pin pair is not controlled by Fault Input A
bit 1 FAEN2: Fault Input A Enable bit
1 = PWM2H/PWM2L pin pair is controlled by Fault Input A
0 = PWM2H/PWM2L pin pair is not controlled by Fault Input A
bit 0 FAEN1: Fault Input A Enable bit
1 = PWM1H/PWM1L pin pair is controlled by Fault Input A
0 = PWM1H/PWM1L pin pair is not controlled by Fault Input A
Legend:
R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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