© 2004 Microchip Technology Inc. DS70049C-page 2-15
Section 2. CPU
CPU
2
Register 2-2: CORCON: Core Control Register (Continued)
bit 2 PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Bit can be cleared
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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