dsPIC30F Family Reference Manual
DS70063C-page 16-6 © 2004 Microchip Technology Inc.
Register 16-1: QEICON: QEI Control Register (Continued)
bit 2 POSRES: Position Counter Reset Enable bit
1 = Index Pulse resets Position Counter
0 = Index Pulse does not reset Position Counter
(Bit only applies when QEIM<2:0> = 100 or 110)
bit 1 TQCS: Timer Clock Source Select bit
1 = External clock from pin QEA (on the rising edge)
0 = Internal clock (T
CY)
bit 0 UDSRC: Position Counter Direction Selection Control bit
1 = QEB pin State Defines Position Counter Direction
0 = Control/Status bit, UPDN (QEICON<11>), Defines Timer Counter (POSCNT) direction
Note: When configured for QEI mode, control bit is a ‘don’t care’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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