© 2004 Microchip Technology Inc. DS70063C-page 16-7
Section 16. Quadrature Encoder Interface (QEI)
Quadrature Encoder
Interface (QEI)
16
Register 16-2: DFLTCON: Digital Filter Control Register (dsPIC30F6010 Only)
Upper Byte:
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —CEID
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
QEOUT QECK<2:0> INDOUT INDCK<2:0>
bit 7 bit 0
bit 15-9 Unimplemented: Read as ‘0’
bit 8 CEID: Count Error Interrupt Disable bit
1 = Interrupts due to position count errors disabled
0 = Interrupts due to position count errors enabled
bit 7 QEOUT: QEA/QEB Digital Filter Output Enable bit
1 = Digital filter outputs enabled
0 = Digital filter outputs disabled (Normal pin operation)
bit 6-4 QECK<2:0>: QEA/QEB Digital Filter Clock Divide Select bits
111 = 1:256 Clock Divide
110 = 1:128 Clock Divide
101 = 1:64 Clock Divide
100 = 1:32 Clock Divide
011 = 1:16 Clock Divide
010 = 1:4 Clock Divide
001 = 1:2 Clock Divide
000 = 1:1 Clock Divide
bit 3 INDOUT: Index Channel Digital Filter Output Enable bit
1 = Digital filter output is enabled
0 = Digital filter output is disabled (Normal pin operation)
bit 2-0 INDCK<2:0>: Index Channel Digital Filter Clock Divide Select bits
111 = 1:256 Clock Divide
110 = 1:128 Clock Divide
101 = 1:64 Clock Divide
100 = 1:32 Clock Divide
011 = 1:16 Clock Divide
010 = 1:4 Clock Divide
001 = 1:2 Clock Divide
000 = 1:1 Clock Divide
Note: The available control bits in the DFLTCON Register may vary depending on the dsPIC30F device
that is used. Refer to Register 16-2 and Register 16-3 for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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