Microchip Technology dsPIC30F - Page 360

dsPIC30F Family Reference Manual
DS70063C-page 16-8 © 2004 Microchip Technology Inc.
Register 16-3: DFLTCON: Digital Filter Control Register (All dsPIC30F devices except dsPIC30F6010)
Upper Half:
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — IMV<1:0> CEID
bit 15 bit 8
Lower Half:
R/W-0 R/W-0 U-0 U-0 U-0 U-0
QEOUT QECK<2:0>
— — — —
bit 7 bit 0
bit 15-11 Unimplemented: Read as ‘0’
bit 10-9 IMV<1:0>: Index Match Value – These bits allow the user to specify the state of the QEA and QEB input
pins during an Index pulse when the POSCNT register is to be reset.
In 4X Quadrature Count Mode:
IMV1= Required State of Phase B input signal for match on index pulse
IMV0= Required State of Phase A input signal for match on index pulse
In 2X Quadrature Count Mode:
IMV1= Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B)
IMV0= Required State of the selected Phase input signal for match on index pulse
bit 8 CEID: Count Error Interrupt Disable
1 = Interrupts due to count errors are disabled
0 = Interrupts due to count errors are enabled
bit 7 QEOUT: QEA/QEB/INDX pin Digital Filter Output Enable
1 = Digital filter outputs enabled
0 = Digital filter outputs disabled (normal pin operation)
bit 6-4 QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits
111 = 1:256 Clock Divide
110 = 1:128 Clock Divide
101 = 1:64 Clock Divide
100 = 1:32 Clock Divide
011 = 1:16 Clock Divide
010 = 1:4 Clock Divide
001 = 1:2 Clock Divide
000 = 1:1 Clock Divide
bit 3-0 Unimplemented: Read as ‘0’
Note: The available control bits in the DFLTCON Register may vary depending on the dsPIC30F device
that is used. Refer to Register 16-2 and Register 16-3 for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
y = Value set from configuration bits on POR or BOR