© 2004 Microchip Technology Inc. DS70064C-page 17-23
Section 17. 10-bit A/D Converter
10-bit A/D
Converter
17
17.12.2.3 Multiple Channels with Sequential Sampling
As shown in Figure 17-9 when using sequential sampling, the sample time precedes each
conversion time. In the example, 3 T
AD clocks are added for sample time for each channel.
Figure 17-9: Converting 4 Channels, Auto-Sample Start, T
AD Conversion Start, Sequential Sampling
17.12.2.4 Sample Time Considerations Using Clocked Conversion Trigger and Automatic Sampling
Different sample/conversion sequences provide different available sampling times for the S/H
channel to acquire the analog signal. The user must ensure the sampling time exceeds the
sampling requirements, as outlined in Section 17.16 “A/D Sampling Requirements”.
Assuming that the module is set for automatic sampling and using a clocked conversion trigger,
the sampling interval is determined by the sample interval specified by the SAMC bits.
If the SIMSAM bit specifies simultaneous sampling or only one channel is active, the sampling
time is the period specified by the SAMC bit.
Equation 17-3: Available Sampling Time, Simultaneous Sampling
If the SIMSAM bit specifies sequential sampling, the total interval used to convert all channels is
the number of channels times the sampling time and conversion time. The sampling time for an
individual channel is the total interval minus the conversion time for that channel.
Equation 17-4: Available Sampling Time, Simultaneous Sampling
TCONV
ADCLK
ch1_samp
ch2_samp
ch3_samp
ch0_samp
ADRES(0)
ADRES(1)
ADRES(2)
ADRES(3)
TCONV
TCONV TCONV
TCONV
SAMP
TSAMP
TSAMP
DONE
= 0
TSEQ = Channels per Sample (CH/S) *
((SAMC<4:0> * T
AD) + Conversion Time (TCONV))
T
SMP =(TSEQ – TCONV)
Note 1: CH/S specified by CHPS<1:0> bits.
2: T
SEQ is the total time for the sample/convert sequence.
TSMP = SAMC<4:0> * TAD
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